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rev. b a ad7470/ad7472 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? 2003 analog devices, inc. all rights reserved. 1.75 msps, 4 mw 10-bit/12-bit parallel adcs functional block diagram t/h 10-/12-bit successive approximation adc output drivers ad7470/ad7472 v in convst agnd dgnd av dd dv dd ref in v drive db9 (db11) db0 clk in cs rd busy control logic ad7470 is a 10-bit part with db0 to db9 as outputs. ad7472 is a 12-bit part with db0 to db11 as outputs. features specified for v dd of 2.7 v to 5.25 v 1.75 msps for ad7470 (10-bit) 1.5 msps for ad7472 (12-bit) low power ad7470: 3.34 mw typ at 1.5 msps with 3 v supplies 7.97 mw typ at 1.75 msps with 5 v supplies ad7472: 3.54 mw typ at 1.2 msps with 3 v supplies 8.7 mw typ at 1.5 msps with 5 v supplies wide input bandwidth 70 db typ snr at 500 khz input frequency flexible power/throughput rate management no pipeline delays high speed parallel interface sleep mode: 50 na typ 24-lead soic and tssop packages general description the ad7470/ad7472 are 10-bit/12-bit high speed, low power, successive approximation adcs. the parts operate from a single 2.7 v to 5.25 v power supply and feature throughput rates up to 1.5 msps for the 12-bit ad7472 and up to 1.75 msps for the 10-bit ad7470. the parts contain a low noise, wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 1 mhz. the conversion process and data acquisition are controlled using standard control inputs, allowing easy interfacing to microprocessors or dsps. the input signal is sampled on the falling edge of convst , and conversion is also initiated at this point. busy goes high at the start of conversion and goes low 531.66 ns after falling edge of convst (ad7472 with a clock frequency of 26 mhz) to indicate that the con- version is complete. there are no pipeline delays associated with the parts. the conversion result is accessed via standard cs and rd signals over a high speed parallel interface. t he ad7470/ad7472 use advanced design techniques to a chieve very low power dissipation at high throug hput rates. with 3 v supplies and 1.5 msps throughput rates, the ad7470 typically consumes, on average, just 1.1 ma. with 5 v supplies and 1.75 msps, the average current consumption is typically 1.6 ma. the part also offers flexible power/throughput rate management. operating the ad7470 with 3 v supplies and 50 0 ksps throughput reduces the current consumption to 713 a. at 5 v supplies and 500 ksps, the part consumes 944 a. it is also possible to operate the parts in an auto sleep mode, where the part wakes up to do a conversion and automatically enters sleep mode at the end of conversion. this method allows very low power dissipation numbers at lower throughput rates. in this mode, the ad7472 can be operated with 3 v supplies at 100 ksps, and consume an average current of just 124 a. at 5 v supplies and 100 ksps, the average current consumption is 171 a. the analog input range for the part is 0 v to ref in. the 2.5 v reference is applied externally to the ref in pin. the conver- sion rate is determined by the externally-applied clock. product highlights 1. hi gh throughput with low power consumption. the ad7470 offers 1.75 msps throughput and the ad7472 o ffers 1.5 msps throughput rates with 4 mw power consumption. 2. flexible power/throughput rate management. the conver- sion rate is determined by an externally-applied clock allow- ing the power to be reduced as the conversion rate is reduced. t he part also features an auto sleep mode to maximize power efficiency at lower throughput rates. 3. no pipeline delay. the part features a standard successive approximation adc with accurate control of the sampling instant via a convst input and once off conversion control.
rev. b ad7470/ad7472 ? ad7470?pecifications 1 (v dd = 2.7 v to 5.25 v 2 , ref in = 2.5 v, f clkin = 30 mhz @ 5 v and 24 mhz @ 3 v; t a = t min to t max 3 , unless otherwise noted.) parameter a version 1 unit test conditions/comments dynamic performance 5 v 3 v f s = 1.75 msps @ 5 v, f s = 1.5 msps @ 3 v signal to noise + distortion (sinad) 60 60 db min f in = 500 khz sine wave 60 60 db min f in = 100 khz sine wave signal-to-noise ratio (snr) 60 60 db min f in = 500 khz sine wave 60 60 db min f in = 100 khz sine wave total harmonic distortion (thd) ?3 83 db typ f in = 500 khz sine wave ?5 75 db max f in = 100 khz sine wave peak harmonic or spurious noise (sfdr) 85 85 db typ f in = 500 khz sine wave ?5 75 db max f in = 100 khz sine wave intermodulation distortion (imd) second-order terms ?9 75 db typ f in = 500 khz sine wave ?5 75 db max f in = 100 khz sine wave third-order terms ?7 75 db typ f in = 500 khz sine wave ?5 75 db max f in = 100 khz sine wave aperture delay 5 5 ns typ aperture jitter 15 15 ps typ full power bandwidth 20 20 mhz typ @ 3 db dc accuracy f s = 1.75 msps @ 5 v; f s = 1.5 msps @ 3 v resolution 10 10 bits integral nonlinearity 1 1 lsb max differential nonlinearity 0.9 0.9 lsb max guaranteed no missed codes to 10 bits offset error 2.5 2.5 lsb max gain error 1 1 lsb max analog input input voltage ranges 0 to ref in 0 to ref in v dc leakage current 1 1 a max input capacitance 33 33 pf typ reference input ref in input voltage range 2.5 2.5 v 1% for specified performance dc leakage current 1 1 a max input capacitance 10/20 10/20 pf typ track-and-hold mode logic inputs input high voltage, v inh 2.4 2.4 v min input low voltage, v inl 0.4 0.4 v max input current, i in 1 1 a max typically 10 na, v in = 0 v or v dd input capacitance, c in 4 10 10 pf max logic outputs output high voltage, v oh v drive 0.2 v drive 0.2 v min i source = 200 a output low voltage, v ol 0.4 0.4 v max i sink = 200 a floating-state leakage current 10 10 a max v dd = 2.7 v to 5.25 v floating-state output capacitance 10 10 pf max output coding straight (natural) binary conversion rate conversion time 12 12 clk in cycles (max) track-and-hold acquisition time 135 135 ns min throughput rate 1.75 1.5 msps max conversion time + acquisition time clk in of 30 mhz @ 5 v and 24 mhz @ 3 v power requirements v dd +2.7/+5.25 v min/max i dd 5 digital inputs = 0 v or dv dd normal mode 2.4 ma max v dd = 4.75 v to 5.25 v; f s = 1.75 msps; typ 2 ma quiescent current 900 a max v dd = 4.75 v to 5.25 v; f s = 1.75 msps normal mode 1.5 ma max v dd = 2.7 v to 3.3 v; f s = 1.5 msps; typ 1.3 ma quiescent current 800 a max v dd = 2.7 v to 3.3 v; f s = 1.5 msps sleep mode 1 a max clk in = 0 v or dv dd power dissipation 5 digital inputs = 0 v or dv dd normal mode 12 mw max v dd = 5 v 4.5 mw max v dd = 3 v sleep mode 5 w max v dd = 5 v; clk in = 0 v or dv dd 3 w max v dd = 3 v; clk in = 0 v or dv dd notes 1 temperature ranges as follows: a version: ?0 c to +85 c. 2 the ad7470 functionally works at 2.35 v. typical specifications @ 25 c for snr (100 khz) = 59 db; thd (100 khz) = ?4 db; inl 0.8 lsb. 3 the ad7470 will typically maintain a-grade performance up to 125 c, with a reduced clk of 20 mhz @ 5 v and 16 mhz @ 3 v. typical sleep mode current @ 125 c is 700 na. 4 sample tested @ 25 c to ensure compliance. 5 see power vs. throughput rate section. specifications subject to change without notice.
rev. b ? ad7470/ad7472 ad7472?pecifications 1 (v dd = 2.7 v to 5.25 v 2 , ref in = 2.5 v, a and b versions: f clkin = 26 mhz @ 5 v and 20 mhz @ 3 v, t a = t min to t max , unless otherwise noted.) parameter a version 1 b version 1 unit test conditions/comments dynamic performance 5 v 3 v 5 v3 v f s = 1.5 msps @ 5 v, f s = 1.2 msps @ 3 v signal to noise + distortion (sinad) 69 69 69 69 db typ f in = 500 khz sine wave 68 68 68 68 db min f in = 100 khz sine wave signal-to-noise ratio (snr) 70 70 70 70 db typ f in = 500 khz sine wave 68 68 68 68 db min f in = 100 khz sine wave total harmonic distortion (thd) ?3 ?8 ?3 ?8 db typ f in = 500 khz sine wave ?3 ?4 ?3 ?4 db typ f in = 100 khz sine wave ?5 ?5 ?5 ?5 db max f in = 100 khz sine wave peak harmonic or spurious noise (sfdr) 86 81 86 81 db typ f in = 500 khz sine wave ?6 ?6 ?6 ?6 db typ f in = 100 khz sine wave ?6 ?6 ?6 ?6 db max f in = 100 khz sine wave intermodulation distortion (imd) second-order terms ?7 ?7 ?7 ?7 db typ f in = 500 khz sine wave ?6 ?6 ?6 ?6 db typ f in = 100 khz sine wave third-order terms ?7 ?7 ?7 ?7 db typ f in = 500 khz sine wave ?6 ?6 ?6 ?6 db typ f in = 100 khz sine wave aperture delay 5 5 5 5 ns typ aperture jitter 15 15 15 15 ps typ full power bandwidth 20 20 20 20 mhz typ @ 3 db dc accuracy f s = 1.5 msps @ 5 v , f s = 1.2 msps @ 3 v resolution 12 12 12 12 bits integral nonlinearity 2 2 1 1 lsb max guaranteed no missed codes to 11 bits (a version) differential nonlinearity 1.8 1.8 0.9 0.9 lsb max guaranteed no missed codes to 12 bits (b version) offset error 10 10 10 10 lsb max gain error 2 2 2 2 lsb max analog input input voltage ranges 0 to ref in 0 to ref in 0 to ref in 0 to ref in v dc leakage current 1 1 1 1 a max input capacitance 33 33 33 33 pf typ reference input ref in input voltage range 2.5 2.5 2.5 2.5 v 1% for specified performance dc leakage current 1 1 1 1 a max input capacitance 10/20 10/20 10/20 10/20 pf typ track-and-hold mode logic inputs input high voltage, v inh 2.4 2.4 2.4 2.4 v min input low voltage, v inl 0.4 0.4 0.4 0.4 v max input current, i in 1 1 1 1 a max typically 10 na, v in = 0 v or v dd input capacitance, c in 3 10 10 10 10 pf max logic outputs output high voltage, v oh v drive 0.2 v drive 0.2 v drive 0.2 v drive 0.2 v min i source = 200 a output low voltage, v ol 0.4 0.4 0.4 0.4 v max i sink = 200 a floating-state leakage current 10 10 10 10 a max v dd = 2.7 v to 5.25 v floating-state output capacitance 10 10 10 10 pf max output coding straight (natural) binary straight (natural) binary conversion rate conversion time 14 14 14 14 clk in cycles (max) track-and-hold acquisition time 135 135 135 135 ns min throughput rate 1.5 1.2 1.5 1.2 msps max conversion time + acquisition time power requirements v dd +2.7/+5.25 +2.7/+5.25 v min/max i dd 4 digital inputs = 0 v or dv dd normal mode 2.4 2.4 ma max v dd = 4.75 v to 5.25 v; typ 2 ma; f s = 1.5 msps quiescent current 900 900 a max v dd = 4.75 v to 5.25 v; f s = 1.5 msps normal mode 1.5 1.5 ma max v dd = 2.7 v to 3.3 v; typ 1.3 ma; f s = 1.2 msps quiescent current 800 800 a max v dd = 2.7 v to 3.3 v; f s = 1.2 msps sleep mode 1 1 a max clk in = 0 v or dv dd power dissipation 4 digital inputs = 0 v or dv dd normal mode 12 12 mw max v dd = 5 v 4.5 4.5 mw max v dd = 3 v sleep mode 5 5 w max v dd = 5 v; clk in = 0 v or dv dd 33 w max v dd = 3 v; clk in = 0 v or dv dd notes 1 temperature ranges as follows: a and b versions: ?0 c to +85 c. 2 the ad7472 functionally works at 2.35 v. typical specifications @ 25 c for snr (100 khz) = 68 db; thd (100 khz) = ?4 db; inl 0.8 lsb. 3 sample tested @ 25 c to ensure compliance. 4 see power vs. throughput rate section. specifications subject to change without notice.
rev. b ? ad7470/ad7472 ad7472?pecifications 1 (v dd = 2.7 v to 5.25 v 2 , ref in = 2.5 v,y version: f clkin = 20 mhz @ 5 v and 14 mhz @ 3 v; t a = t min to t max , unless otherwise noted.) parameter y version 1 unit test conditions/comments dynamic performance 5 v 3 v f s = 1.2 msps @ 5 v, f s = 875 ksps @ 3 v signal to noise + distortion (sinad) 69 69 db typ f in = 500 khz sine wave 68 68 db min f in = 100 khz sine wave signal-to-noise ratio (snr) 70 70 db typ f in = 500 khz sine wave 68 68 db min f in = 100 khz sine wave total harmonic distortion (thd) ?3 ?8 db typ f in = 500 khz sine wave ?3 ?4 db typ f in = 100 khz sine wave ?5 ?5 db max f in = 100 khz sine wave peak harmonic or spurious noise (sfdr) 86 81 db typ f in = 500 khz sine wave ?6 ?6 db typ f in = 100 khz sine wave ?6 ?6 db max f in = 100 khz sine wave intermodulation distortion (imd) second-order terms ?7 ?7 db typ f in = 500 khz sine wave ?6 ?6 db typ f in = 100 khz sine wave third-order terms ?7 ?7 db typ f in = 500 khz sine wave ?6 ?6 db typ f in = 100 khz sine wave aperture delay 5 5 ns typ aperture jitter 15 15 ps typ full power bandwidth 20 20 mhz typ @ 3 db dc accuracy f s = 1.2 msps @ 5 v; f s = 875 ksps @ 3 v resolution 12 12 bits integral nonlinearity 2 2 lsb max differential nonlinearity 1.8 1.8 lsb max guaranteed no missed codes to 11 bits offset error 10 10 lsb max gain error 2 2 lsb max analog input input voltage ranges 0 to ref in 0 to ref in v dc leakage current 1 1 a max input capacitance 33 33 pf typ reference input ref in input voltage range 2.5 2.5 v 1% for specified performance dc leakage current 1 1 a max input capacitance 10/20 10/20 pf typ track-and-hold mode logic inputs input high voltage, v inh 2.4 2.4 v min input low voltage, v inl 0.4 0.4 v max input current, i in 1 1 a max typically 10 na, v in = 0 v or v dd input capacitance, c in 3 10 10 pf max logic outputs output high voltage, v oh v drive 0.2 v drive 0.2 v min i source = 200 a output low voltage, v ol 0.4 0.4 v max i sink = 200 a floating-state leakage current 10 10 a max v dd = 2.7 v to 5.25 v floating-state output capacitance 10 10 pf max output coding straight (natural) binary conversion rate conversion time 14 14 clk in cycles (max) track-and-hold acquisition time 140 140 ns min throughput rate 1200 875 ksps max conversion time + acquisition time power requirements v dd +2.7/+5.25 v min/max i dd 4 digital inputs = 0 v or dv dd normal mode 2.4 ma max v dd = 4.75 v to 5.25 v; f s = 1.2 msps; typ 2 ma quiescent current 900 a max v dd = 4.75 v to 5.25 v; f s = 1.2 msps normal mode 1.5 ma max v dd = 2.7 v to 3.3 v; f s = 875 ksps; typ 1.3 ma quiescent current 800 a max v dd = 2.7 v to 3.3 v; f s = 875 ksps sleep mode 2 a max clk in = 0 v or dv dd power dissipation 4 digital inputs = 0 v or dv dd normal mode 12 mw max v dd = 5 v 4.5 mw max v dd = 3 v sleep mode 10 w max v dd = 5 v; clk in = 0 v or dv dd 6 w max v dd = 3 v; clk in = 0 v or dv dd notes 1 temperature ranges as follows: y version: ?0 c to +125 c. 2 the ad7472 functionally works at 2.35 v. typical specifications @ 25 c for snr (100 khz) = 68 db; thd (100 khz) = ?4 db; inl 0.8 lsb. 3 sample tested @ 25 c to ensure compliance. 4 see power vs. throughput rate section. specifications subject to change without notice.
rev. b ? ad7470/ad7472 limit at t min , t max parameter ad7470 ad7472 unit description f clk 2 10 10 khz min 30 26 mhz max t convert 436.42 531.66 ns min t clk = 1/f clk in t wakeup 11 s max wake-up time t 1 10 10 ns min convst pulse width t 2 convst to busy delay, 10 10 ns max v dd = 5 v, a and b versions 15 ns max v dd = 5 v, y version 30 30 ns max v dd = 3 v, a and b versions 35 ns max v dd = 3 v, y version t 3 00 ns max busy to cs setup time t 4 3 00 ns max cs to rd setup time t 5 20 20 ns min rd pulse width t 6 3 15 15 ns min data access time after falling edge of rd t 7 4 88 ns max bus relinquish time after rising edge of rd t 8 00 ns max cs to rd hold time t 9 acquisition time 135 135 ns max a and b versions 140 ns max y version t 10 100 100 ns min quiet time notes 1 sample tested at 25 c to ensure compliance. all input signals are specified with tr = tf = 5 ns (10% to 90% of v dd ) and timed from a voltage level of 1.6 v. see figure 1. 2 mark/space ratio for the clk inputs is 40/60 to 60/40. first clk pulse should be 10 ns min from falling edge of convst . 3 measured with the load circuit of figure 1 and defined as the time required for the output to cross 0.8 v or 2.0 v. 4 t 7 is derived from the measured time taken by the data outputs to change 0.5 v when loaded with the circuit of figure 1. the measured number is then extrapolated back to remove the effects of charging or discharging the 50 pf capacitor. this means that the time, t 7 , quoted in the timing characteristics, is the true bus relinquish time of the part and is independent of the bus loading. specifications subject to change without notice. timing specifications 1 (v dd = 2.7 v to 5.25 v, ref in = 2.5 v; t a = t min to t max , unless otherwise noted.) 200 a i ol 200 a i oh c l 50pf to output pin 1.6v figure 1. load circuit for digital output timing specifications
rev. b ad7470/ad7472 ? ordering guide temperature resolution package package model range (bits) options 1 description ad7470aru ?0 c to +85 c1 0 ru-24 tssop ad7470aru-reel ?0 c to +85 c1 0 ru-24 tssop ad7470aru-reel7 ?0 c to +85 c1 0 ru-24 tssop ad7472ar ?0 c to +85 c1 2 r-24 soic ad7472ar-reel ?0 c to +85 c1 2 r-24 soic ad7472ar-reel7 ?0 c to +85 c1 2 r-24 soic ad7472aru ?0 c to +85 c1 2 ru-24 tssop ad7472aru-reel ?0 c to +85 c1 2 ru-24 tssop ad7472aru-reel7 ?0 c to +85 c1 2 ru-24 tssop ad7472br ?0 c to +85 c1 2 r-24 soic ad7472br-reel ?0 c to +85 c1 2 r-24 soic ad7472bru ?0 c to +85 c1 2 ru-24 tssop ad7472bru-reel ?0 c to +85 c1 2 ru-24 tssop ad7472bru-reel7 ?0 c to +85 c1 2 ru-24 tssop ad7472yr ?0 c to +125 c1 2 r-24 soic ad7472yr-reel ?0 c to +125 c1 2 r-24 soic ad7472yru ?0 c to +125 c1 2 ru-24 tssop ad7472yru-reel ?0 c to +125 c1 2 ru-24 tssop ad7472yru-reel7 ?0 c to +125 c1 2 ru-24 tssop EVAL-AD7470CB 2 evaluation board eval-ad7472cb 2 evaluation board eval control brd2 3 controller board notes 1 r = soic; ru = tssop. 2 this can be used as a standalone evaluation board or in conjunction with the eval-control board for evaluation/demonstration pu rposes. 3 this board is a complete unit allowing a pc to control and communicate with all analog devices evaluation boards ending in the cb designators. to order a complete evaluation kit, you need to order the specific adc evaluation board, for example, eval-ad7472cb, the eval c ontrol brd2, and a 12 v ac transformer. see the relevant evaluation board application note for more information. absolute maximum ratings 1 (t a = 25 c unless otherwise noted.) av dd to agnd/dgnd . . . . . . . . . . . . . . . . . ?.3 v to +7 v dv dd to agnd/dgnd . . . . . . . . . . . . . . . . . ?.3 v to +7 v v drive to agnd/dgnd . . . . . . . . . . . . . . . . ?.3 v to +7 v av dd to dv dd . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +0.3 v v drive to dv dd . . . . . . . . . . . . . . . ?.3 v to dv dd + 0.3 v agnd to dgnd . . . . . . . . . . . . . . . . . . . . ?.3 v to +0.3 v analog input voltage to agnd . . . . ?.3 v to av dd + 0.3 v digital input voltage to dgnd . . . . ?.3 v to dv dd + 0.3 v ref in to agnd . . . . . . . . . . . . . . . ?.3 v to av dd + 0.3 v input current to any pin except supplies 2 . . . . . . . . 10 ma operating temperature range commercial (a and b versions) . . . . . . . . . ?0 c to +85 c industrial (y version) . . . . . . . . . . . . . . . ?0 c to +125 c storage temperature range . . . . . . . . . . . ?5 c to +150 c caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad7470/ad7472 features proprietary esd protection circuitry, permanent dam- age may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150 c ja thermal impedance . . . . . . . . . . . . . . . 75 c/w (soic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 c/w (tssop) jc thermal impedance . . . . . . . . . . . . . . . 25 c/w (soic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 c/w (tssop) lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 c esd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 kv notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 transient currents of up to 100 ma will not cause scr latch-up.
rev. b ad7470/ad7472 ? pin configurations top view (not to scale) 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 ad7470 nc = no connect db7 db6 db8 db5 (msb) db9 db4 av dd v drive ref in dv dd v in dgnd agnd db3 cs db2 rd db1 convst db0 (lsb) clkin nc busy nc top view (not to scale) 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 ad7472 db9 db8 db10 db7 (msb) db11 db6 av dd v drive ref in dv dd v in dgnd agnd db5 cs db4 rd db3 convst db2 clkin db1 busy db0 (lsb) pin function descriptions mnemonic function cs chip select. active low logic input used in conjunction with rd to access the conversion result. the conversion result is placed on the data bus following the falling edge of both cs and rd . cs and rd are both connected to the same and gate on the input so the signals are interchangeable. cs can be hardwired permanently low. rd read input. logic input used in conjunction with cs to access the conversion result. the conversion result is placed on the data bus following the falling edge of both cs and rd . cs and rd are both connected to same and gate on the input so the signals are interchangeable. cs and rd can be hardwired permanently low, in which case the data bus is always active and the result of the new conversion is clocked out slightly before to the busy line going low. convst conversion start input. logic input used to initiate conversion. the input track-and-hold amplifier goes from track mode to hold mode on the falling edge of convst , and the conversion process is initiated at this point. the conversion input can be as narrow as 10 ns. if the convst input is kept low for the duration of conversion and is still low at the end of conversion, the part will autom atically enter sleep mode. if the part enters this sleep mode, the next rising edge of convst wakes up the part. wake-up time for the part is typically 1 s. clk in master clock input. the clock source for the conversion process is applied to this pin. conversion time for the ad7472 takes 14 clock cycles, and conversion time for the ad7470 takes 12 clock cycles. the frequency of this master clock input, therefore, determines the conversion time and achievable throughput rate. while the adc is not converting, the clock-in pad is in three-state and thus no clock is going through the part. busy busy output. logic output indicating the status of the conversion process. the busy signal goes high after the falling edge of convst and stays high for the duration of conversion. once conversion is complete and the con- version result is in the output register, the busy line returns low. the track-and-hold returns to track mode just prior to the falling edge of busy, and the acquisition time for the part begins when busy goes low. if the convst input is still low when busy goes low, the part automatically enters its sleep mode on the falling edge of busy. ref in reference input. an external reference must be applied to this input. the voltage range for the external reference is 2.5 v 1% for specified performance. av dd analog supply voltage, 2.7 v to 5.25 v. this is the only supply voltage for all analog circuitry on the ad7470/ ad7472. the av dd and dv dd voltages should ideally be at the same potential and must not be more than 0.3 v apart even on a transient basis. this supply should be decoupled to agnd. dv dd digital supply voltage, 2.7 v to 5.25 v. this is the supply voltage for all digital circuitry on the ad7470/ ad7472 aside from the output drivers. the dv dd and av dd voltages should ideally be at the same potential and must not be more than 0.3 v apart even on a transient basis. this supply should be decoupled to dgnd. agnd analog ground. ground reference point for all analog circuitry on the ad7470/ad7472. all analog input signals and any external reference signal should be referred to this agnd voltage. the agnd and dgnd voltages should ideally be at the same potential and must not be more than 0.3 v apart even on a transient basis.
rev. b ad7470/ad7472 ? pin function descriptions (continued) mnemonic function dgnd digital ground. this is the ground reference point for all digital circuitry on the ad7470 and ad7472. the dgnd and agnd voltages should ideally be at the same potential and must not be more than 0.3 v apart even on a transient basis. v in analog input. single-ended analog input channel. the input range is 0 v to ref in. the analog input presents a high dc input imped ance. v drive supply voltage for the output drivers, 2.7 v to 5.25 v. this voltage determines the output high voltage for the data output pins. it allows av dd and dv dd to operate at 5 v (and maximize the dynamic performance of the (adc), while the digital outputs can interface to 3 v logic. db0?b9/11 data bit 0 to data bit 9 (ad7470) and db11 (ad7472). parallel digital outputs that provide the conversion result for the part. these are three-state outputs that are controlled by cs and rd . the output high voltage level for these outputs is determined by the v drive input.
rev. b ad7470/ad7472 ? terminology integral nonlinearity this is the maximum deviation from a straight line passing through the endpoints of the adc transfer function. the end- points of the transfer function are zero scale, a point 1/2 lsb below the first code transition, and full scale, a point 1/2 lsb above the last code transition. differential nonlinearity this is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. offset error this is the deviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal, i.e., agnd + 0.5 lsb. gain error the last transition should occur at the analog value 1.5 lsb below the nominal full scale. the first transition is a 0.5 lsb above the low end of the scale (zero in the case of ad7470/ ad7472). the gain error is the deviation of the actual difference between the first and last code transitions from the ideal differ- ence between the first and last code transitions with offset errors removed. track-and-hold acquisition time the track-and-hold amplifier returns into track mode after the end of conversion. track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within 1 lsb, after the end of conversion. signal to (noise + distortion) ratio this is the measured ratio of signal to (noise + distortion) at the output of the a/d converter. the signal is the rms amplitude of the fundamental. noise is the sum of all nonfundamental sig- nals up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. the theoretical signal to (noise + distortion) ratio for an ideal n-bit converter with a sine wave input is given by signal to ( noise + distortion ) = (6.02 n + 1.76) db thus for a 12-bit converter, this is 74 db and for a 10-bit con- verter is 62 db. total harmonic distortion (thd) total harmonic distortion is the ratio of the rms sum of har- monics to the fundamental. for the ad7470/ad7472 it is defined as thd db vvvvv v () log () = ++++ 20 2 2 3 2 4 2 5 2 6 2 1 where v 1 is the rms amplitude of the fundamental and v 2 , v 3 , v 4 , v 5, and v 6 are the rms amplitudes of the second through the sixth harmonics. peak harmonic or spurious noise peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2 and excluding dc) to the rms value of the fundamental. normally, the value of this specification is deter- mined by the largest harmonic in the spectrum, but for adcs where the harmonics are buried in the noise floor, it will be a noise peak. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, etc. intermodulation distortion terms are those for which neither m nor n is equal to zero. for example, the second-order terms include (fa + fb) and (fa ?fb), while the third-order terms include (2fa + fb), (2fa ?fb), (fa + 2fb) and (fa ?2fb). the ad7470/ad7472 are tested using the ccif standard where two input frequencies near the top end of the input band- width are used. in this case, the second-order terms are usually distanced in frequency from the original sine waves while the third-order terms are usually at a frequency close to the input frequencies. as a result, the second- and third-order terms are specified separately. the calculation of the intermodulation distortion is as per the thd specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dbs. aperture delay in a sample-and-hold, the time required after the hold command for the switch to open fully is the aperture delay. the sample is, in effect, delayed by this interval, and the hold command would have to be advanced by this amount for precise timing. aperture jitter a perture jitter is the range of variation in the aperture delay. in other words, it is the uncertainty about when the sample is taken. jitter is the result of noise which modulates the phase of the hold command. this specification establishes the ulti- mate timing error, hence the maximum sampling frequency for a given resolution. this error will increase as the input dv/dt increases.
rev. b ad7470/ad7472 ?0 circuit description converter operation the ad7470/ad7472 are 10-bit/12-bit successive approxima- tion analog-to-digital converters based around a capacitive dac. the ad7470/ad7472 can convert analog input signals in the range 0 v to v ref . figure 2 shows a very simplified sche- matic of the adc. the control logic, sar, and the capacitive dac are used to add and subtract fixed amounts of charge from the sam pling capacitor to bring the comparator back into a balanced condition. capacitive dac switches sar control logic comparator output data 10-/12-bit parallel v in v ref control inputs figure 2. simplified block diagram of ad7470/ad7472 figure 3 shows the adc during its acquisition phase. sw2 is closed and sw1 is in position a. the comparator is held in a balanced condition and the sampling capacitor acquires the signal on v in . comparator v in control logic capacitive dac agnd 2k sw2 sw1 a b figure 3. adc acquisition phase figure 4 shows the adc during conversion. when conversion starts, sw2 will open and sw1 will move to position b, causing the comparator to become unbalanced. the adc then runs through its successive approximation routine and brings the comparator back into a balanced condition. when the compara- tor is rebalanced, the conversion result is available in the sar register. comparator v in control logic capacitive dac agnd 2k sw2 sw1 a b figure 4. adc conversion phase typical connection diagram figure 5 shows a typical connection diagram for the ad7470/ ad7472. conversion is initiated by a falling edge on convst . once convst goes low, the busy signal goes high, and at the end of conversion, the falling edge of busy is used to acti- vate an interrupt service routine. the cs and rd lines are then activ ated in parallel to read the 10- or 12-data bits. the recom- mended ref in voltage is 2.5 v providing an analog input range of 0 v to 2.5 v, making the ad7470/ad7472 a unipolar adc. it is recommended to perform a dummy conversion after power-up as the first conversion result could be incorrect. this also ensures that the part is in the correct mode of operation. the convst pin should not be floating when power is applied as a rising edge on convst might not wake up the part. in figure 5 the v drive pin is tied to dv dd , which results in logic output voltage values being either 0 v or dv dd . the voltage applied to v drive controls the voltage value of the output logic signals. for example, if dv dd is supplied by a 5 v supply and v drive by a 3 v supply, the logic output voltage levels w ould be either 0 v or 3 v. this feature allows the ad7470/ad7472 to interface to 3 v parts while still enabling the adc to process signals at 5 v supply. 10 f 0.1 f paralled interface 2.5v * * recommended ref in voltage 0v to ref in 1nf 10 f 0.1 f 47 f ad7470/ ad7472 av dd v drive dv dd ref in db0 db9 (db11) cs busy convst rd v in c/ p analog supply 2.7v?.25v ++ figure 5. typical connection diagram
rev. b ad7470/ad7472 ?1 adc transfer function the output coding of the ad7470/ad7472 is straight binary. the designed code transitions occur midway between succes- sive integer lsb values (0.5 lsb, 1.5 lsb, etc). the lsb size is equal to (ref in)/4096 for the ad7472 and to (ref in)/1024 for the ad7470. the i deal transfer characteristic for the ad7472 is shown in figure 6. 111...111 111...110 111...000 011...111 000...010 000...001 000...000 adc code 0v 0.5lsb v ref ?.5lsb analog input 1lsb = v ref /4096 figure 6. transfer characteristic for 12 bits ac acquisition time in ac applications it is recommended to always buffer analog input signals. the source impedance of the drive circuitry must be kept as low as possible to minimize the acquisition time of the adc. large values of impedance at the v in pin of the adc will cause the thd to degrade at high input frequencies. the ad8021, ad8047, ad8051, ad9631, and ad797 are some of the op amps that could be used to buffer the analog input. figure 7 shows the ad7470/ad7472 performance for some of those recommended input buffers. typical amplifier input snr thd current buffers 500khz 500khz consumption ad8047 70 78 5.8ma ad9631 69.5 80 17ma ad8051 68.6 78 4.4ma ad797 70 84 8.2ma ad7470/ad7472 dynamic performance specifications figure 7. recommended input buffers reference input th e following references are best suited for use with the ad7470/ad7472. adr291 ad780 ref192 adr421 for optimum performance, a 2.5 v reference is recommended. the parts can function with a reference up to 3 v and down to 2 v, but the performance deteriorates. dc acquisition time the adc starts a new acquisition phase at the end of a conver- sion and ends it on the falling edge of the convst signal. at the end of conversion there is a settling time associated with the sampling circuit. this settling time lasts approximately 135 ns. the analog signal on v in is also being acquired during this settling time; therefore, the minimum acquisition time needed is approximately 135 ns. figure 8 shows the equivalent charging circuit for the sampling capacitor when the adc is in its acquisition phase. r3 repre- sents the source impedance of a buffer amplifier or resistive network, r1 is an internal switch resistance, r2 is for bandwidth control, and c1 is the sampling capacitor. c2 is back-plate capacitance and switch parasitic capacitance. during the acquisition phase the sampling capacitor must be charged to within 1 lsb of its final value. r3 r1 125 v in c1 22pf c2 8pf r2 636 figure 8. equivalent sampling circuit analog input figure 9 shows the equivalent circuit of the analog input struc- ture of the ad7470/ad7472. the two diodes, d1 and d2, provide esd protection for the analog inputs. the capacitor c3 is typically about 4 pf and can be primarily attributed to pin capacitance. the resistor r1 is an internal switch resistance. this resistor is typically about 125 ? . the capacitor c1 is the sampling capacitor, while r2 is used for bandwidth control. r1 125 v in c1 22pf c2 8pf r2 636 d1 d2 c3 4pf v dd figure 9. equivalent analog input circuit clock sources the max clk specification for the ad7470 is 30 mhz, and for the ad7472, it is 26 mhz. these frequencies are not standard off-the-shelf oscillator frequencies. many manufacturers pro- duce oscillator modules close to these frequencies; a typical one being 25.175 mhz from iqd limited. ael crystals limited produces a 25 mhz oscillator module in various packages. crys- tal oscillator manufacturers will produce 26 mhz and 30 mhz oscillators to order. of course any clock source can be used, not just crystal oscillators.
rev. b ad7470/ad7472 ?2 parallel interface the parallel interfaces of the ad7470 and ad7472 are 10 bits and 12 bits wide, respectively. the output data buffers are acti- vated when both cs and rd are logic low. at this point, the con- tents of the data register are placed onto the data bus. figure 10 shows the timing diagram for the parallel port. figure 11 shows the timing diagram for the parallel port when cs and rd are tied permanently low. in this setup, once busy line goes from high to low, the conversion process is completed. the data is available on the output bus slightly before the falling edge of busy. it is important to point out that data bus cannot change state while the adc is doing a conversion as this would have a detri- mental effect on the conversion in progress. the data out lines will go three-state again when either the rd or the cs line goes high. thus the cs can be tied low permanently, leaving the rd line to control conversion result access. refer to v drive section for output voltage levels. t 2 t convert t 3 t 4 t 8 t 5 t 6 t 7 t 9 t 10 busy cs rd dbx convst * * convst should go high when the clk is high or before the first clk cycle. figure 10. parallel port timing t 2 t convert t 9 convst * busy dbx data n data n + 1 * convst should go high when the clk is high or before the first clk cycle. figure 11. parallel port timing with cs and rd tied low t 2 t 3 t 4 t 8 t 6 t 7 clk in convst busy cs rd db x t wakeup t 5 t convert figure 12. wake-up timing diagram (burst clock)
rev. b ad7470/ad7472 ?3 operating modes the ad7470 and ad7472 have two possible modes of opera- tion, depending on the state of the convst pulse at the end of a conversion, mode 1 and mode 2. there is a continuous clock on the clkin pin. mode 1 (high speed sampling) in this mode of operation, the convst pulse is brought high before the end of conversion i.e., before busy goes low (see figure 10). if the convst pin is brought from high to low while busy is high, the conversion is restarted. when operat- ing in this mode, a new conversion should not be initiated until the acquisition time has elapsed after busy goes low. this acquisition time allows the track-and-hold circuit to accurately acquire the input signal. as mentioned earlier, a read should not be done during a conversion. this mode facilitates the fastest throughput times for the ad7470/ad7472. mode 2 (sleep mode) figure 13 shows ad7470/ad7472 in mode 2 operation where the adc goes into sleep mode after conversion. the convst line is brought low to initiate a conversion and remains low until after the end of conversion. if convst goes high and low again while busy is high, the conversion is restarted. o nce the busy line goes from a high to a low, the convst line has its status checked and, if low, the part enters sleep mode. the device wakes up again on the rising edge of the convst signal. there is a wake-up time of typically 1 s after the rising edge of convst before the busy line can go high to indicate s tart of conversion. busy will only go high once convst goes low. the convst line can go from a high to a low during this wake-up time, but the conversion will still not be initiated until after the 1 s wake-up time. superior power performance can be achieved in this mode of operation by waking up the ad7470 and ad7472 only to carry out a conversion. burst mode burst mode on the ad7470/ad7472 is a subsection of mode 1 and mode 2; the clock is noncontinuous. figure 12 shows how the adc works in burst mode for mode 2. the clock needs to be switched on only during conversion, a minimum of 12 clock cycles for the ad7470 and 14 clock cycles for the ad7472. because the clock is off during nonconverting intervals, system pow er is saved. the busy signal can be used to gate the clkin pulses. the adc does not begin the conversion process until convst busy cs rd dbx t wakeup t convert figure 13. mode 2 operation the first clkin rising edge after busy goes high. the clock needs to start less than two clock cycles away from the convst active edge, otherwise inl deteriorates. for example, if the clock frequency is 28 mhz, the clock must start within 71.4 ns of convst going low. in figure 12, the a/d converter section is put into sleep mode once conversion is completed. on the rising edge of convst , it is woken up again. the user must be wary of the wake-up time because it will reduce the sampling rate of the adc. v drive the v drive pin is used as the voltage supply to the output driv- ers and is a separate supply from av dd and dv dd . the purpose of using a separate supply for the output drivers is that the user can vary the output high voltage, v oh , from the v dd supply to the ad7470/ad7472. for example, if av dd and dv dd is using a 5 v supply, the v drive pin can be powered from a 3 v supply. the adc has better dynamic performance at 5 v than at 3 v, so operating the part at 5 v, while still being able to interface to 3 v parts, pushes the ad7470/ad7472 to the top bracket of high performance 10-bit/12-bit adcs. of course, the adc can have its v drive and dv dd pins connected together and be pow- ered from a 3 v or 5 v supply. all outputs are powered from v drive . these are all the data out pins and the busy pin. the convst , cs , rd , and clkin signals are related to the dv dd voltage. power-up it is recommended that the user perform a dummy conversion after power-up, because the first conversion result could be incorrect. this also ensures that the part is in the correct mode of operation. the recommended power-up sequence is as follows: 1. gnd 4. digital inputs 2. v dd 5. ref in 3. v drive 6. v in power vs. throughput the two modes of operation for the ad7470 and ad7472 will produce different power versus throughput performances, mode 1 and mode 2; see operating modes section of the data sheet for more detailed descriptions of these modes. mode 2 is the s leep mode of the part and it achieves the optimum power performance.
rev. b ad7470/ad7472 ?4 mode 1 figure 14 shows the ad7472 conversion sequence in mode 1 using a throughput rate of 500 ksps and a clock frequency of 26 mhz. at 5 v supply, the current consumption for the part when converting is typically 2 ma, and the quiescent current is typically 650 a. the conversion time of 531.66 ns contributes 2.658 mw to the overall power dissipation in the following way: (531.66 ns /2 s ) (5 2 ma ) = 2.658 mw the contribution to the total power dissipated by the remaining 1.468 s of the cycle is 2.38 mw. (1.468 s /2 s ) (5 650 a ) = 2.38 mw thus the power dissipated during each cycle is 2.658 mw + 2.38 mw = 5.038 mw convst busy 531.66ns 1.468 s 2 s t convert t quiescent figure 14. mode 1 power dissipation mode 2 figure 15 shows the ad7472 conversion sequence in mode 2 using a throughput rate of 500 ksps and a clock frequency of 26 mhz. at 5 v supply, the current consumption for the part when converting is typically 2 ma, while the sleep current is 1 a max. the power dissipated during this power-down is negli- gible, and is thus not worth considering in the total power fig- ure. during the wake-up phase, the ad7472 will draw 650 a typically. overall power dissipated is 531 66 2 5 2 1 2 5 650 4 283 ./ / . ns s ma s s a mw ??? () () + () () = convst busy t wakeup 531.66ns 1.468 s 2 s 1 s t convert t quiescent figure 15. mode 2 power dissipation tpc 1 sand tpc 2 show a typical graphical representation of power vs. throughput for the ad7472 when in (a) mode 1 @ 5 v and 3 v and mode 2 @ 5 v and 3 v
t ypical performance characteristics?d7470/ad7472 throughput (khz) 8 4 0 50 300 power (mw) 1500 1300 1100 1000 800 600 7 3 6 2 5 1 5v 3v tpc 1. power vs. throughput (mode 1 @ 5 v and 3 v) throughput (khz) 4 0 50 100 power (mw) 750 700 650 600 300 200 7 3 6 2 5 1 150 350 250 400 450 500 550 5v 3v tpc 2. power vs. throughput (mode 2 @ 5 v and 3 v) code 1.0 0 ?.0 0 inl error (lsb) 4096 ?.8 3584 3072 2560 2048 1536 1024 512 ?.6 ?.4 ?.2 0.2 0.4 0.6 0.8 tpc 3. typical inl for 2.75 v @ 25 c code 1.0 0 ?.0 0 dnl error (lsb) 4096 ?.8 3584 3072 2560 2048 1536 1024 512 ?.6 ?.4 ?.2 0.2 0.4 0.6 0.8 tpc 4. typical dnl for 2.75 v @ 25 c input frequency (khz) 72 62 52 10 snr + d (db) 2000 54 1000 500 200 100 50 56 58 60 64 66 68 70 ad7472 5v ad7472 3v ad7470 5v ad7470 3v tpc 5. typical snr + d vs. input tone input frequency (khz) 90 75 50 10 thd (db) 2000 55 1000 500 200 100 50 60 65 70 80 85 ad7472 5v ad7472 3v ad7470 5v ad7470 3v tpc 6. typical thd vs. input tone
rev. b ad7470/ad7472 ?6 supply (v) 69.2 2.50 snr (db) 2.75 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25 69.4 69.6 69.8 70.0 70.2 70.4 70.6 +85 c +25 c ?0 c tpc 7. typical snr vs. supply frequency (khz) ?20 0 db 100 200 300 400 500 600 ?00 ?0 ?0 ?0 ?0 0 tpc 8. typical snr @ 500 khz input tone frequency (khz) ?.8 10 db 100 1000 10000 100000 ?.3 ?.8 ?.3 ?.8 ?.3 ?.8 0.2 ?.3 5v 3v tpc 9. typical bandwidth
rev. b ad7470/ad7472 ?7 grounding and layout the analog and digital power supplies are independent and separately pinned out to minimize coupling between the analog and digital sections within the device. to complement the excel- lent noise performance of the ad7470/ad7472, it is imperative that care be given to the pcb layout. figure 16 shows a recom- mended connection diagram for the ad7470/ad7472. all of the ad7470/ad7472 ground pins should be soldered directly to a ground plane to minimize series inductance. the av dd , dv dd , and v drive pins should be decoupled to both the analog and digital ground planes. the large value capacitors will decouple low frequency noise to analog ground; the small value capacitors will decouple high frequency noise to digital ground. all digital circuitry power pins should be decoupled to the digital ground plane. the use of ground planes can physically separate sensitive analog components from the noisy digital system. the two ground planes should be joined in only one place and should not overlap so as to minimize capacitive coupling betw een them. if the ad7470/ad7472 is in a system where multiple devices require agnd to dgnd connections, the connection should still be made at one point only, a star ground point, which should be established as close as possible to the ad7470/ad7472. noise can be minimized by applying some simple rules to the pcb layout: analog signals should be kept away from digital signals; fast switching signals like clocks should be shielded with digital ground to avoid radiating noise to other sections of the board and clock signals should never be run near the analog inputs; avoid running digital lines under the device as these will c ouple noise onto the die; the power supply lines to the ad7470/ ad7472 should use as large a trace as possible to provide a low impedance path and reduce the effects of glitches on the power supply line; avoid crossover of digital and analog signals and pl ace traces that are on opposite sides of the board at right angles to each other. noise to the analog power line can be further reduced by use of multiple decoupling capacitors as shown in figure 16. decou- pling capacitors should be placed directly at the power inlet to the pcb and also as close as possible to the power pins of the ad7470/ad7472. the same decoupling method should be used on other ics on the pcb, with the capacitor leads as short as possible to minimize lead inductance. power supplies separate power supplies for av dd and dv dd are desirable but, if necessary, dv dd may share its power connection to av dd . t he digital supply (dv dd ) must not exceed the analog supply (av dd ) by more than 0.3 v in normal operation. microprocessor interfacing ad7470/ad7472 to adsp-2185 interface f igure 17 shows a typical interface between the ad7470/ad7472 and the adsp-2185. the adsp-2185 processor can be used in one of two memory modes, full memory mode and host mode. the mode c pin determines in which mode the processor works. the interface in figure 17 is set up to have the processor work- ing in full memory mode, which allows full external addressing capabilities. when the ad7470/ad7472 has finished converting, the busy line requests an interrupt through the irq2 pin. the irq2 interrupt has to be set up in the interrupt control register as edge-sensitive. the dms (data memory select) pin latches in the address of the adc into the address decoder. the read operation is thus started. address decoder ad7470/ ad7472 * adsp-2185 * a0?15 dms irq2 rd mode c d0?23 convst cs rd busy db0?b9 (db11) address bus data bus 100k * additional pins omitted for clarity optional figure 17. interfacing to the adsp-2185 ad7470/ad7472 to adsp-21065 interface figure 18 shows a typical interface between the ad7470/ad7472 and the adsp-21065l sharc processor. this interface is an example of one of three dma handshake modes. the ms x ad7470/ ad7472 ad780 10 f + 1nf v in v out 1nf + 10 f 0.1 f 10 f dv dd agnd dgnd v drive v ref av dd + 0.1 f47 f analog supply 5v + 0.1 f figure 16. decoupling circuit
rev. b ad7470/ad7472 ?8 control line is actually three memory select lines. internal addr 25?4 are decoded into ms 3-0 ; these lines are then asserted as chip selects. the dmar 1 (dma request 1) is used in this setup as the interrupt to signal end of conversion. the rest of the interface is standard handshaking operation. ad7470/ ad7472 * adsp-21065l * addr 0 ?ddr 23 rd d0?31 convst rd busy db0?b9 (db11) address bus data bus * additional pins omitted for clarity optional dmar 1 address latch address bus address decoder ms x cs figure 18. interfacing to adsp-21065l ad7470/ad7472 to tms320c25 interface figure 19 shows an interface between the ad7470/ad7472 and the tms320c25. the convst signal can be applied from the tms320c25 or from an external source. the busy line interrupts the digital signal processor when conversion is completed. the tms320c25 does not have a separate rd output to drive the ad7470/ad7472 rd input directly. this has to be generated from the processor strb and r/ w outputs with the addition of some glue logic. the rd signal is or-gated with the msc signal to provide the wait state required in the read cycle for correct interface timing. the following instruction is used to read the conversion from the ad7470/ad7472: in d,adc where d is data memory address and adc is the ad7470/ ad7472 address. the read operation must not be attempted during conversion. address decoder ad7470/ ad7472 * tms320c25 * a0?15 is strb r/ w ready dmd0?md15 convst cs rd busy db0?b9 (db11) address bus * additional pins omitted for clarity optional msc data bus figure 19. interfacing to the tms320c25 ad7470/ad7472 to pic17c4x interface figure 20 shows a typical parallel interface between the ad7470/ ad7472 and the pic17c42/43/44. the microcontroller sees the adc as another memory device with its own specific memory address on the memory map. the convst signal can be controlled by either the microcontroller or an external source. the b usy signal provides an interrupt request to the microcontroller w hen a conversion ends. the int pin on the pic17c42/43/44 must be configured to be active on the nega- tive edge. portc and portd of the microcontroller are bidirectional and used to address the ad7470/ad7472 and also to read in the 10-bit (ad7470) or 12-bit (ad7472) data. the oe pin on the pic can be used to enable the output buffers on the ad7470/ad7472 and to perform a read operation. * additional pins omitted for clarity address decoder address latch optional pic17c4x * ad0?d15 oe int ad7470/ ad7472 * convst cs rd busy db0?b9 (db11) ale figure 20. interfacing to the pic17c4x ad7470/ad7472 to 80c186 interface figure 21 shows the ad7470/ad7472 interfaced to the 80c186 microprocessor. the 80c186 dma controller provides two independent high speed dma channels where data transfer can occur between memory and i/o spaces. (the ad7470/ ad7472 occupies one of these i/o spaces.) each data trans- fer consumes two bus cycles, one cycle to fetch data and the other to store data. after the ad7470/ad7472 has finished conversion, the busy line generates a dma request to channel 1 (drq1). as a result of the interrupt, the processor performs a dma read opera- tion which also resets the interrupt latch. sufficient priority must be assigned to the dma channel to ensure that the dma request will be serviced before the completion of the next con- version. this configuration can be used with 6 mhz and 8 mhz 80c186 processors. 80c186 * ad0?d15 a16?19 rd drq1 address/data bus data bus * additional pins omitted for clarity address latch address bus address decoder ale r s q ad7470/ ad7472 * convst rd busy db0?b9 (db11) optional cs figure 21. interfacing to the 80c186
rev. b ad7470/ad7472 ?9 outline dimensions 24-lead standard small outline package [soic] wide body (r-24) dimensions shown in millimeters and (inches) controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design compliant to jedec standards ms-013ad 8 0 0.75 (0.0295) 0.25 (0.0098) 45 1.27 (0.0500) 0.40 (0.0157) seating plane 0.30 (0.0118) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 1.27 (0.0500) bsc 24 13 12 1 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 15.60 (0.6142) 15.20 (0.5984) coplanarity 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) 24-lead thin shrink small outline package [tssop] (ru-24) dimensions shown in millimeters 24 13 12 1 6.40 bsc 4.50 4.40 4.30 pin 1 7.90 7.80 7.70 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 seating plane compliant to jedec standards mo-153ad 0.10 coplanarity
rev. b ad7470/ad7472 ?0 c01127??0/03(b) revision history location page 10/03?ata sheet changed from rev. a to rev. b. added y version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . universal changes to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 changes to timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 changes to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 changes to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 changes to pin function descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 changes to offset error description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 changes to gain error description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 changes to operating modes section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 changes to power-up section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 relabeled tpc captions and renumbered subsequent figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

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